PhotonForge

FREE TO START. BUILT TO SCALE.
NOTHING TO SWITCH.

The only AI-powered end-to-end photonic design platform currently available.

Supported foundry PDKs

AIM Photonics Bifrost Communications Fraunhofer GlobalFoundries imec Ligentec LXT Tower Semiconductor
Why Use PhotonForge
The photonics industry is full of point tools - one for layout, one for simulation, one for circuit, and one for PDK. Every hand-off between tools costs time, introduces errors, and loses context. PhotonForge solves this challenge using an end-to-end design platform that connects layout, simulation, circuit analysis, foundry PDKs, and AI assistance in one environment.
FREE
Layout
Python-first PIC layout, hierarchical design, routing automation, DRC/LVS verification, GDS/OASIS interoperability
Foundry & PDK
Native integration with leading foundry PDKs for tape-out-ready designs
Simulation
GPU-accelerated multi-physics solvers — FDTD, Mode, EME, Heat, Charge, RF, up to 500× faster
Circuit & System
Compact model generation, S-matrix circuit simulation, eye diagram analysis, time-domain system modeling
Photonic Canvas (GUI)
Schematic editor GUI, GUI PDK Support, PDA SDK, Connector to EDA ecosystem and open access database
Why PhotonForge Layout Is Different
PhotonForge Layout is FREE to use. It is the same environment where you will run GPU-accelerated simulations, manage foundry PDKs, and analyze complete systems when you are ready. Start where you are. Scale when you need to.
Capability Other Free Layout Tools PhotonForge Layout (Free) Example
Design model Geometry and GDS output only Hierarchical, netlist-driven layout, virtual/physical connections, and connectivity built into the object model Design Model
Routing Manual or basic routing Algorithmic routing automation - S-bend, Manhattan, taper, and schematic-driven layout conversion Routing
Scripting Standalone Python scripting Python-first API fully addressable end-to-end, including routing, netlist extraction, and simulation setup Scripting
Verification Requires separate tools DRC/LVS hooks integrated into the day-to-day workflow, not a disconnected signoff step LVS
Interoperability GDS export only Full GDS/OASIS import/export with hierarchy preserved. Cadence OpenAccess connector for enterprise environments DRC
Scalability Python-only, limited at scale C++-accelerated core engine built for production-scale chip layouts Scalability
Path Forward Dead end - requires switching tools for simulation, PDK, or circuit work Seamless continuity into the further tiers (Simulation, Circuit, PDK, AI Agent) - no tool switch, no re-learning, no data migration Path Forward
AI Readiness Not designed for agentic workflows AI-native by architecture - every layout operation is API-addressable, ready for agentic AI workflows today AI Readiness